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RMII(Reduced Media Independent Interface)

Ethernet MAC和PHY之间通讯的一种接口，MII的精简版本，线减半时钟翻倍，最高支持100Mbps。

原理图设计

RMII信号连接如下图（图中PHY的TX和RX按按照MAC侧定义的，即MAC的TX应连接PHY的RX，MAC的RX连接PHY的TX）：

RMII各信号的定义见下表：

Table 8: RMII Signal Definitions
Signal Name	Source	Description
REF_CLK	Switch/MAC or External	Reference Clock.This clock is sourced externally or by the MAC and is always 50 MHz.Both the MAC and the PHY have the same data and control signals on the rising edge of this clock.
TXEN	Switch/MAC	Transmit Enable.Active high single indicating that the current 2-bit data on TXD[1:0]is valid.
TXD[1:0]	Switch/MAC	Transmit Data.2-bit transmit data bus.
CRS_DV	PHY	Carrier Sense/Receive Data Valid.Active high signal indicating that the media is non-idle and that the current data on the RXD[1:0]is valid.
RXD[1:0]	PHY	Receive Data.2-bit receive data bus.
RXER	PHY	Receive Error.Active high signal instructing the MAC that a packet error has been detected.
MDC	Switch/MAC	Management Data Clock.
MDIO	Bidirectional	Management Data.