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RGMII(Reduced Gigabit Media Independent Interface)

Ethernet MAC和PHY之间通讯的一种接口，GMII的精简接口，最高支持1000Mbps。

常用标准

V2.0相对于V1.3引入了CLK Delay，具体的调测减文档： TI RGMII Interface Timing Budgets

RGMII信号连接如下图（图中PHY的TX和RX按按照MAC侧定义的，即MAC的TX应连接PHY的RX，MAC的RX连接PHY的TX）：

RGMII各信号的定义见下表：

Table 12: RGMII Signal Definitions
Signal Name	Source	Description
GTXCLK	Switch/MAC	Transmit Clock.This clock is 125 MHz in 1000BASE-T mode,25 MHz in 100BASE- TX mode,and 2.5 MHz in 10BASE-T mode.
TXEN (TXEN/TXER)	Switch/MAC	Transmit Control.This signal has a number of functions multiplexed onto it.
		·TXEN=Transmit Enable.This information is presented on the rising edge of the transmit clock in RGMIl mode.
		·TXER=Transmit Error.This information is presented on the falling edge of the transmit clock in RGMIl mode.
TXD[3:0]	Switch/MAC	Transmit Data.Data bits TXD[3:0]are presented on the rising edge of the transmit clock in both RGMII.Data bits TXD[7:4]are presented on the falling edge of the transmit clock in RGMIl mode.
RXC	PHY	Receive Clock.This clock is 125 MHz in 1000BASE-T mode,25 MHzin 100BASE-TX mode,and 2.5 MHz in 10BASE-T mode.
RXDV (RXDV/RXER)	PHY	Receive Control.This signal has a number of functions multiplexed onto it.
		·RXDV=Receive Data Valid.This information is presented on the rising edge of the receive clock in RGMIl mode.
		·RXER=Receive Error.This information is presented on the falling edge of the receive clock in RGMIl mode.
RXD[3:0]	PHY	Receive Data.Data bits RXD[3:0]are presented on the rising edge of the receive and data bits RXD[7:4]are presented on the falling edge of the receive clock.
MDC	Switch/MAC	Management Data Clock.
MDIO	Both	Management Data.