Ethernet MAC和PHY之间数据传递的一种MII(Media Independent Interface)接口,,GMII的精简接口,时钟不变,但在时钟上升和下降沿均收发数据,最高支持1000Mbps。
Reduced Gigabit Media Independent Interface (RGMII) 4/1/2002 Version 2.0
Reduced Gigabit Media Independent Interface (RGMII) 12/10/2000 Version 1.3
V2.0相对于V1.3引入了CLK Delay,具体的调测见文档: TI RGMII Interface Timing Budgets
RGMII信号连接如下图(图中PHY的TX和RX按按照MAC侧定义的,即MAC的TX应连接PHY的RX,MAC的RX连接PHY的TX):
RGMII各信号的定义见下表:
Table 12: RGMII Signal Definitions | ||
Signal Name | Source | Description |
GTXCLK | Switch/MAC | Transmit Clock.This clock is 125 MHz in 1000BASE-T mode,25 MHz in 100BASE- TX mode,and 2.5 MHz in 10BASE-T mode. |
TXEN (TXEN/TXER) | Switch/MAC | Transmit Control.This signal has a number of functions multiplexed onto it. |
·TXEN=Transmit Enable.This information is presented on the rising edge of the transmit clock in RGMIl mode. |
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·TXER=Transmit Error.This information is presented on the falling edge of the transmit clock in RGMIl mode. |
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TXD[3:0] | Switch/MAC | Transmit Data.Data bits TXD[3:0]are presented on the rising edge of the transmit clock in both RGMII.Data bits TXD[7:4]are presented on the falling edge of the transmit clock in RGMIl mode. |
RXC | PHY | Receive Clock.This clock is 125 MHz in 1000BASE-T mode,25 MHzin 100BASE-TX mode,and 2.5 MHz in 10BASE-T mode. |
RXDV (RXDV/RXER) | PHY | Receive Control.This signal has a number of functions multiplexed onto it. |
·RXDV=Receive Data Valid.This information is presented on the rising edge of the receive clock in RGMIl mode. |
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·RXER=Receive Error.This information is presented on the falling edge of the receive clock in RGMIl mode. |
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RXD[3:0] | PHY | Receive Data.Data bits RXD[3:0]are presented on the rising edge of the receive and data bits RXD[7:4]are presented on the falling edge of the receive clock. |
MDC | Switch/MAC | Management Data Clock. |
MDIO | Both | Management Data. |
电平转换:RGMII电平一般有1.8V、2.5V和3.3V三种,MAC和PHY尽量配置成同样的电平,避免使用电平转换芯片。如果电平无法一致,因其时钟频率高,三极管或MOS管的电平转换电路不满足此频率要求,需要用专门的转换芯片。TI提供的电平转换芯片见文档“ Voltage Translation Buying Guide”。