MII（Media Independent Interface）
Ethernet MAC和PHY之间数据传递的一种MII（Media Independent Interface）接口，最高支持100Mbps。
常用标准
IEEE 802.3u (Fast Ethernet Specification)： 802.3-2022 第22卷
原理图设计
MII信号连接如下图（图中PHY的TX和RX按按照MAC侧定义的，即MAC的TX应连接PHY的RX，MAC的RX连接PHY的TX）：
MII各信号的定义见下表：
| Table 7: MII Signal Definitions | ||
| Signal Name | Source | Description |
| TXC | PHY | Transmit Clock.This clock is sourced bythe PHY and is25 MHz for 100 Mbps mode and 2.5 MHz for 10 Mbps mode.The PHY samples TXD on the rising edge of TXC. |
| TXEN | Switch/MAC | Transmit Enable.Active high single indicating that the current nibble on TXD is valid |
| TXD[3:0] | Switch/MAC | Transmit Data.Nibble-wide transmit data. |
| TXER | Switch/MAC | Transmit Error.Active high signal instructing the PHY to transmit an errored symbol |
| RXC | PHY | Receive Clock.This clock is sourced by the PHY and is 25 MHz for 100 Mbps mode and 2.5 MHz tor 10 Mbps mode.Ine MAC samples KXD on tne rising eage of KXC. |
| RXDV | PHY | Receive Data Valid.Active high signal indicating that the current nibble on RXD is valid |
| RXD[3:0] | PHY | Receive Data.Nibble-wide receive data. |
| RXER | PHY | Receive Error.Active high signal instructing the MAC that a packet error has been detected. |
| CRS | PHY | Carrier Sense.Active high signal indicating activity on the media. |
| COL | PHY | Collision.Active high signal indicating that a collision has occurred on the media. |
| MDC | Switch/MAC | Management Data Clock. |
| MDIO | Bidirectional | Management Data. |
电平转换：MII电平一般有1.8V、2.5V和3.3V三种，MAC和PHY尽量配置成同样的电平，避免使用电平转换芯片。如果电平无法一致，因其时钟频率高，三极管或MOS管的电平转换电路不满足此频率要求，需要用专门的转换芯片。TI提供的电平转换芯片见文档“ Voltage Translation Buying Guide”。